In power applications involving an integrated circuit control element, an inductive load is typically driven by a power field effect transistor (FET). When the FET is turned off, the inductive load will have a fly-back voltage associated therewith due to the inductive storage of energy therein. This fly-back will cause the voltage on the drain of an N-channel FET utilized for the driving element to rise to a relatively high level. Voltage excursions that exceed the junction breakdown voltage of an FET, can damage the FET.
In order to protect the FET, a clamp circuit is typically connected between the drain and gate of the FET. When the voltage on the drain of the FET rises to a sufficiently high level, current will conduct through the clamp, pulling the gate of the FET high and turning on the FET, this effectively prevents the fly-back voltage from pulling the drain above the clamp voltage. Conventional clamp circuits use a series of Zener diodes, each having a breakdown voltage that, when added together, comprise the overall threshold voltage for the clamp.
One disadvantage to prior art clamp circuits is the current level that must be accommodated by the clamp. Whenever the fly-back voltage pulls the drain of the FET high, current will flow from the drain to the gate, some passing through the driving circuit that drives the FET. This is a finite amount of current, which can be sufficiently high to require relatively robust components in the clamp. Therefore, the design of a clamp circuit that will accommodate the necessary current levels requires relatively large devices. This can become a disadvantage in that the clamp circuits are typically incorporated into the integrated circuit that drives the FET.
An exemplary external FET driving circuit having a drain-to-gate clamp in accordance with the conventional design will now be described with reference to FIG. 1.
Circuit 100 includes a driver portion 102, a drain-to-gate clamp portion 104 and an inductive load portion 106. Driver portion 102 includes a driver 108, a positive current source 110, a negative current source 112, a positive side current mirror 114, a negative side current mirror 116. Positive current source 110 includes a first current source 118 and switch 120, whereas negative current source 112 includes a second current source 122 and a switch 124. Positive side current mirror 114 includes P-channel FET 126 and P-channel FET 128, whereas negative side current mirror 116 includes N-channel FET 130 and N-channel FET 132. Driver portion 102 provides a driving signal to node 144 to drive the gate of an external FET 148. The drain of FET 148 is connected to an inductive load portion 142, whereas the source of FET 148 is connected to ground.
Drain-to-gate clamp portion 104 includes a diode 134, Zener diode 136, Zener diode 138 and resistor 140. Clamp portion 104 is used to prevent FET 148 from being damaged by fly-back-induced voltage excursions.
Inductive load portion 106 includes an inductor 142. Inductive load 106 represents the external applied element driven by FET 148 in power application.
In this design, the voltage-clamp is achieved by utilizing a Zener diode stack together with a forward biased diode and a resistor. During the fly-back, a large inductor current is generated and this current flows into the Zener diode stack. Therefore, most of the current is dissipated by the diodes and is used to counteract the gate-driver current. Once the current in the Zener diode stack exceeds the gate-driver current, the gate-driver output voltage starts to increase and turns on the external FET. This, in turn, allows dissipating some of the inductor current and prevents exceeding the drain-to-gate breakdown voltage. This implementation will be described in more detail below.
In operation, in general, driver portion 102 provides a driving signal to the gate of external FET 148 via node 144. When external FET is turned OFF, an inductive load as provided by inductor 142 will have a fly-back voltage. This fly-back voltage creates a first current path that flows through drain-to-gate clamp portion 104 to ground. In such an instance, drain-to-gate clamp portion 104 turns on FET 148, which then provides a second current path to ground for the fly-back voltage to prevent damage to external FET 148. A more detailed discussion of the operation is described below.
In operation, driver 108 receives an input signal 150 and generates ON and OFF signals to control current source 110 and 112. In this example, a portion of input signal 150 is illustrated with high logic state portions 154 and 158 and low logic state portions 152 and 156. In the high logic state portions 154 and 158, driver 108 outputs a high logic signal to positive current source 110 and outputs a low logic signal to negative current source 112. In the low logic state portions 152 and 156, driver 108 outputs a low logic signal to positive current source 110 and outputs a high logic signal to negative current source 112.
When positive current source 110 receives a high logic signal, switch 120 is closed, which electrically connects first current source 118 to positive side current mirror 114, which in turn provides a current Ip1 to P-channel FET 126 of current mirror 114. Current mirror 114 then generates current Ip2 out of P-channel FET 128 from current Ip1. Current Ip1 creates a voltage Vg at node 144. Further, when positive current source 110 receives a high logic signal, negative current source 112 receives a low logic signal. In such a case, switch 124 is opened, which electrically disconnects second current source 122 from negative side current mirror 116.
Alternatively, when negative current source 112 receives a high logic signal, switch 124 is closed, which electrically connects second current source 122 to negative side current mirror 116, in turn provides a current In1 to N-channel FET 130 of current mirror 116. Current mirror 116 then generates current In2 out of N-channel FET 132 from current In1. Further, when negative current source 112 receives a high logic signal, positive current source 110 receives a low logic signal. In such a case, switch 120 is opened, which electrically disconnects first current source 118 from positive side current mirror 114.
The current mirror ratio for both positive side current mirror 114 and negative side current mirror 116 is N:1, where N>1, which achieves high current delivery at node 144.
When external FET 148, connected to inductive load 142, turns Off quickly, a fly-back current IL is experienced. During this event, the drain of FET 148 exhibits a large transient swing that needs to be clamped for drain-to-gate protection of the device. In other words, if the fly-back current flows from the drain of FET 148 to the gate of FET 148, the FET can be damaged. The voltage-clamp is achieved by drain-to-gate clamp portion 104. During the fly-back, a large inductor current IL is generated and this current flows into the drain-to-gate clamp portion 104 as Id. Most of the current is dissipated by Zener diode 136 and Zener diode 138, and is used to counteract the gate-driver current, In2. Once Id exceeds the gate-driver current, In2, the gate-driver output voltage Vg starts to increase. External FET 148 will be turned on after Vg exceeds the threshold voltage of FET 148. This, in turn, allows dissipating some of fly-back current IL by providing a ground path to Iext. Consequently, IL is limited and prevented from exceeding the drain-to-gate breakdown voltage of FET 148.
However, the conventional implementation discussed above requires a very high Id current in order to turn ON external FET 148 efficiently. The reason is that Id must counteract the gate-driver current, either Ip2 or In2, first before it is able to turn on external FET 148. To accommodate high Id current, Zener diode 136 and Zener diode 138 must be of sufficient size for high current flow. As the power consumption is proportional to current and size of the transistor or diode, the requests of high current Id and large size Zener diode 136 and Zener diode 138 result in high power consumption and increased area. Thus, the power consumption problem and increased area associated with the conventional design become more significant problems in high-voltage applications.
What is needed is a FET driving circuit having a drain-to-gate clamp portion that consumes less power and has a smaller area than that of conventional FET driving circuits.